1. Field of the Invention
The present invention generally relates to peripheral component interconnect express (PCI Express) and, more particularly, to a method and device for lane ordering of PCI Express.
2. The Related Art
The standard bus for computer peripherals has evolved from the early ISA interface, EISA interface, PCI33 interface, to PCI66 interface and PCI133 interface. The PCI associated peripheral devices prevail in recent years.
The peripheral component interconnect express (PCI Express) interface is becoming the standard interface of next generation. PCI Express applies point-to-point transmission. For each end point, each PCI Express lane has a signal transmission pair and a signal receiving pair. For the current specification, PCI express has a differential signal transmission speed as high as 2.5 Gbps. PCI express data tranceiving requires four physical signals, and a plurality of control signals. Compared to PCI, the PCI Express can achieve a higher transmission rate with less physical pins. The PCI Express also defines various hardware specifications, including single lane, 4 lanes, 8 lanes, 16 lanes and 32 lanes, to meet the different bandwidth requirement of various peripheral devices. For example, a graphic card which needs a large bandwidth may use a 32-lane PCI Express interface. The PCI Express can be applied in the north bridge chip or the south bridge chip.
The PCI Express specification defines the termination state of the receiver and the transmitter, including impedance, and common mode voltage, . . . etc. The PCI Express specification also defines two types of lane order, the normal lane order and the reverse lane order. FIG. 1 shows a schematic diagram of a 4-lane PCI Express with the reverse lane order. The four PCI Express lanes on the left connect to the four PCI Express lanes on the right in the reverse order. The two ends are coupled through the 4-lane PCI Express slot (or connection) 100. In other words, the four PCI Express lanes on the left (Lane 0, Lane 1, Lane 2, and Lane 3) are coupled to the four PCI Express lanes on the right (Lane 3, Lane 2, Lane 1, and Lane 0), respectively. In another hardware coupling order, the four PCI Express lanes on the left (Lane 0, Lane 1, Lane 2, and Lane 3) are coupled to the four PCI Express lanes on the right (Lane 0, Lane 1, Lane 2, and Lane 3), respectively. Both coupling orders are accepted by the PCI specification. Nevertheless, various combinations of different IC designers, PCB manufacturers, and peripheral manufacturers may result in various hardware designs. Thus, incorrect PCI Express interconnection fails the final product.